Do you know the reason??
Why the top metal layer is wider than other lower metals in semiconductor process?
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Top Metal Layers (like M7 , M8 , M9 , ...) are made Wider to reduce the Resistance.
But,why only top metal is wide??
If M1,M2,M3,M4,M5 are also wide, All metal would have low resistance?
Lower metals are kept for nets connection that are not conducting heavy current. Top metals are for carrying heavy currents like clock,vdd,vss etc. If we have wider metals in lower levels , we will face issues due to heavy capacitve effects of wide metals. And increasing metal width will increase the area of the cell due to the requirement of more routing area.
Why the top metal layer is wider than other lower metals in semiconductor process?
-->
Top Metal Layers (like M7 , M8 , M9 , ...) are made Wider to reduce the Resistance.
But,why only top metal is wide??
If M1,M2,M3,M4,M5 are also wide, All metal would have low resistance?
Lower metals are kept for nets connection that are not conducting heavy current. Top metals are for carrying heavy currents like clock,vdd,vss etc. If we have wider metals in lower levels , we will face issues due to heavy capacitve effects of wide metals. And increasing metal width will increase the area of the cell due to the requirement of more routing area.
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