KarMic 23

Friday, January 21, 2011

Universal Logic : Mux to Logic gates conversion

1. Designing an Inverter using 2:1 MUX.

2. Designing an AND Gate using 2:1 MUX.

3. Designing an OR Gate using 2:1 MUX.

4. Designing an XOR Gate using 2:1 MUX.

5. Designing an XNOR Gate using 2:1 MUX.

Why the lines of force in an electric field start at the +ve charge and terminate at the -ve charge?

Find the answer at :

http://www.physlink.com/Education/AskExperts/ae245.cfm

Thursday, January 13, 2011

LVCMOS

Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)

is a low voltage class of CMOS technology integrated circuits.To obtain better performance and lower costs, semiconductor manufacturers reduce the device geometries of integrated circuits.With each reduction the associated operating voltage must also be reduced in order to maintain the same basic operational characteristics of the transistors. As semiconductor technology has progressed,LVCMOS power supply voltage and interface standards for decreasing voltages have been defined by the Joint Electron Devices Engineering Council JEDEC for 3.3, 3.0, 2.5, 1.5, 1.2 and 1.0 volts.

Monday, January 10, 2011

CMOS inverting tri-state buffer

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The inverter on the left is required to generate the negated value of the 'enable' input signal. (It can be removed if both the positive and negated value of the 'enable' signal are available from external circuitry.) As shown here, the upper p-channel transistor (driven by the enable input) and the lower n-channel transistor (driven by the inverted enable signal) are conducting whenever the enable input is low. In this case, the inner two transistors are supplied with VCC and GND and behave like a standard inverter. As a result, the tri-state buffer output is the inverted of the data input A.When the enable input is high,both outer transistor are non-conducting, and the tri-state buffer output is floating ('Z').


  nENA  A  | NTRI
 ----------+------
     1  *  | Z  (floating)
     0  0  | 1
     0  1  | 0

The Tri-state Buffer is used in many electronic and microprocessor circuits as they allow multiple logic devices to be connected to the same wire or bus without damage or loss of data. For example,suppose we have a data line or data bus with some memory,peripherals, I/O or a CPU connected to it. Each of these devices is capable of sending or receiving data onto this data bus. If these devices start to send or receive data at the same time a short circuit may occur when one device outputs to the bus a logic "1" the supply voltage,while another is set at logic level "0" or ground, resulting in a short circuit condition and possibly damage to the devices.Then, the Tri-state Buffer can be used to isolate devices and circuits from the data bus and one another.If the outputs of several Tri-state Buffers are electrically connected together Decoders are used to allow only one Tri-state Buffer to be active at any one time while the other devices are in their high impedance state.